View DM74LS299_256916.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
October 1988 Revised March 2000
DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
General Description
The DM74LS299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register.
Features
s Common I/O for reduced pin count s Four operation modes: shift left, shift right, load and store s Separate shift right serial input and shift left serial input for easy cascading s 3-STATE outputs for bus oriented applications
Ordering Code:
Order Number DM74LS299WM DM74LS299N Package Number M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
VCC = Pin 20 GND = Pin 10
Pin Descriptions
Pin Names CP DS0 DS7 S0, S1 MR Description Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset Input (Active LOW)
OE1, OE2 3-STATE Output Enable Inputs (Active LOW) I/O0-I/O7 Parallel Data Inputs or 3-STATE Parallel Outputs Q0-Q7 Serial Outputs
(c) 2000 Fairchild Semiconductor Corporation
DS009827
www.fairchildsemi.com
DM74LS299
Functional Description
The DM74LS299 contains eight edge-triggered D-type flipflops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by the S0 and S1, as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
Mode Select Table
Inputs Response MR S1 S0 CP L H H H H X H L H L X H H L L

X X
Asynchronous Reset; Q0-Q7 = LOW Parallel Load; I/OnQn Shift Right; DS0Q0, Q0Q1, etc. Shift Left; DS7Q7, Q7Q6, etc. Hold
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock (CP) Transition
Logic Diagram
www.fairchildsemi.com
2
DM74LS299
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC MR Pulse Width LOW Recovery Time MR to CP Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW S0 or S1 to CP Hold Time HIGH or LOW S0 or S1 to CP Setup Time HIGH or LOW I/On, DS0, DS7 to CP Hold Time HIGH or LOW I/On, DS0, DS7 to CP CP Pulse Width HIGH or LOW Q0, Q7 I/O0-I/O7 Q0, Q7 I/O0-I/O7 0 24 24 0 0 10 10 0 0 15 15 15 10 Parameter Min 4.75 2 0.8 -0.4 -2.6 8 24 70 Nom 5 Max 5.25 Units V V V mA mA mA mA C ns ns ns ns ns ns ns
3
www.fairchildsemi.com
DM74LS299
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current ICC IOZH IOZL Supply Current 3-STATE Output Off Current HIGH 3-STATE Output Off Current Low
Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max VCC = Min, IOL = Max VIH = Min IOL = 4 mA, VCC = Min VCC = Max VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max, OE = 4.5V VCC = Max VO = 2.7V VCC = Max VO = 0.4V Inputs Sn Sn Inputs Sn Inputs Q0, Q7 I/O0-I/O7 Q0, Q7 I/O0-I/O7
Min
Typ (Note 2) 3.4
Max -1.5
Units V V
2.7 2.4
0.35 0.25
0.5 0.4 0.1 0.2 40 20 -0.8 -0.4
V mA mA A A mA mA mA mA A A
-20 -30
-100 -130 60 40 -400
Switching Characteristics
VCC = +5.0V, TA = +25C RL = 2 k Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Maximum Input Frequency Propagation Delay CP to Q0 or Q7 Propagation Delay CP to I/On Propagation Delay MR to Q0 or Q7 Propagation Delay MR to I/On Output Enable Time 35 26 28 25 35 28 35 18 25 15 20 CL = 15 pF Max MHz ns ns ns ns ns ns Units
www.fairchildsemi.com
4
DM74LS299
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
5
www.fairchildsemi.com
DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

▲Up To Search▲

Price & Availability of DM74LS299

	To Download DM74LS299 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .